This invention relates to a semiconductor memory device, and more particularly a semiconductor memory device controlled in synchronism with an external clock. There has appeared a dynamic random access memory (DRAM) which is synchronous with an external system clock. i.e. a synchronous DRAM (SDRAM) in order to achieve demand of a high-speed random access.
This SDRAM latches either an address or a command applied to each of the pins at a rising edge of an external clock (CLK) and operates internally synchronized to the external clock. An active command is given to the SDRAM synchronized with a clock edge of the external clock CLK. This corresponds to an operation in which /RAS (Row Address Strobe) is changed from high level to low level at DRAM. That is, a word line corresponding to the row address applied to an address pin is selected by an active command to the SDRAM. When a precharging command is given to a SDRAM in synch with a clock edge of the external clock CLK, this corresponds to an operation in which /RAS is changed from a low level to a high level at the general DRAM. That is, Data is restored in the selected memory cell, the selected word line becomes a non-selected one and a node connected between the selected memory cell and the associated bit lines is precharged.
As one of the operation modes of the SDRAM, there is provided a Column Address Strobe (CAS) latency. This is defined by the number of clocks needed or consuming from input of read command to output of the respective read data. Outputing or inputing consecutive addresses during a read cycle or a write cycle is called a burst and a circuit for generating the consecutive addresses is called a burst counter.
In the case of the SDRAM, it is important for increasing a performance how fast consecutive addresses can be read out or written in synch with the external clock CLK, i.e. to what degree a frequency of the external clock CLK can be increased. As a method for increasing an operation frequency, there is provided a 2-bit pre-fetch system. Such a system has a memory cell array (EVEN) of even numbered address and a memory cell arrays (ODD) of odd number addresses, an access for the cell is carried out concurrently for two bits at consecutive addresses and an access of the external input output pins is carried out in a serial manner, thereby increasing the operating frequency.
However, control of reading or writing of such a system is difficult. That is, in a write cycle, after a write command is carried out, two data are latched after being inputed in a serial manner and the latched two data are stored in respective memory cells in parallel at a same time. Such a system needs the time period for latching the two data after the write command is carried out. On the other hand, in read cycle, after the read command is carried out, the consecutive two data are immediately read out. Accordingly, the circuit producing these timings is complex since the timing of writing is different with that of reading. Additional, the writing period is longer than the reading period.